19 research outputs found

    Ripple clock schemes for quantum-dot cellular automata circuits

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    Quantum-dot cellular automata (QCA) is an emerging technology for building digital circuits at nano-scale. It is considered as an alternative to widely used complementary metal oxide semiconductor (CMOS) technology because of its key features, which include low power operation, high density and high operating frequency. Unlike conventional logic circuits in which information is transferred by electrical current, QCA operates with the help of coulomb interaction between two adjacent QCA cells. A QCA cell is a set of four quantum-dots that are placed near the corners of a square. Due to the fact that clocking provides power and control of data flow in QCA, it is considered to be the backbone of QCA operation. This thesis presents the design and simulation of a ripple clock scheme and an enhanced ripple clock scheme for QCA circuits. In the past, different clock schemes were proposed and studied which were focused on data flow in particular direction or reducing delay. This proposed thesis will study the design and simulation of new clock schemes which are more realistic for implementation, give a freedom to propagate logic in all directions, suitable for both combinational and sequential circuits and has potential to support testing and reconfiguration up to some extent. A variety of digital circuits including a 2–to–1 multiplexer, a 1–bit memory, an RS latch, a full adder, a 4–bit adder and a 2–to–4 decoder are implemented and simulated using these clock schemes. A 2–to–4 decoder is used to demonstrate the testing capabilities of these clock schemes. All QCA layouts are drawn and simulated in QCADesigner

    Field-programmable encoding for address-event representation

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    In conventional frame-based image sensors, every pixel records brightness information and sends this information to a receiver serially in a scanning fashion. This full-frame readout approach suffers from high bandwidth requirements and increased power consumption with the increasing size of the pixel array. Event-based image sensors are gaining popularity for reducing the bandwidth and power requirements by sending only meaningful data in an event-driven approach with the help of address-event representation (AER) communication protocol. However, the event-based readout suffers from increased latency and timing error when the number of pixels with an event increase. In this paper, we introduce a new field-programmable AER (FP-AER) encoding scheme which offers benefits of both frame-based and event-based approaches. The readout design can be configured “in the field” using configuration bits. We also compare the performance of the proposed design against existing AER-based approaches for imaging applications and show that FP-AER performs best in both scanning and event-based readout
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